1. Field of the Invention
This invention relates to packaging techniques for integrated circuits and, more particularly, to packaging techniques which minimize the number of bonding pads and package pins used for power and ground conductors without degrading ground bounce and conducted power supply noise performance. This invention also relates to packaging techniques for distribution of power to an integrated circuit and for supplying separate power supplies to for core and peripheral areas of an integrated circuit.
2. Prior Art
To suppress noise due to ground bounce and to suppress noise conducted through the power supply leads of a packaged CMOS integrated circuit, the inductances in the VDD and VSS conductors, that is, the power and ground conductors for a packaged CMOS integrated-circuit, need to be decreased.
Conventional integrated circuit assemblies include an integrated-circuit die, or chip, which is fabricated and later mounted into a package. The package includes a number of pins which are adapted to connect to sockets, circuit boards, and the like. Connections between the integrated-circuit die and the package are made by various wire-bonding techniques. To provide power and ground to a CMOS chip in a conventional pin-grid-array (PGA) package, the base of the PGA package itself includes a VSS ground plane and a VDD power supply plane. Conductive vias are provided through the base of the PGA package to provide connections between the chip and these VSS and VDD planes in the package. Wire bonding is used to connect bonding pads on the chip to the top surface of the conductive vias in the package. These bonding wires have significant inductance values which affect the noise suppression performance of a packaged chip.
A conventional technique for reducing the inductance associated with the power conductors and with the ground conductors for an integrated circuit is to use a large number of additional bonding wires in parallel. These additional parallel bonding wires require a number of additional bonding pads on the integrated circuit chip and a number of additional external connection pins for the package. A disadvantage of this technique is the increase in cost of the packaged integrated circuit due to the increased die size for the additional bonding pads and the increased number of package pins.
Another technique for reducing lead inductance uses so-called "flip-chips." A flip-chip is an integrated circuit chip which has a conductive layer formed on its top surface for supplying VSS and VDD power through appropriately placed vias to the underlying integrated circuit. Also formed on the top of the flip-chip are a number of "solder bumps". The package for a flip chip has two conductive layers formed in the base of the package for providing VSS and VDD power through vias to the top surface of the package. When the chip and the package are assembled together, the chip is flipped upside down so that the solder bumps engage with contact areas on the top surface of the package. The chip and package assembly is then heated to cause the solder bumps to connect the chip to the package. The flip chip package is very expensive because it requires two conductive layers. In comparison with wire-bonding assembly techniques, the flip chip technique of assemblying a chip and a package is more difficult to control than is wirebonding.
Reduction of ground bounce is addressed in an article in the IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988, titled "Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Conduction" by T. Gabara. This article discusses a technique for reducing lead inductances. The technique utilizes an epitaxially deposited conducting substrate which is formed on the back side of a semiconductor die as a VSS conductor plane in order to reduce the number of bonding pads on the die and the number of pins in the package. This technique is limited to reducing the number of power and ground pins in a package by 40-50 percent. Providing a VSS conductor plane on a semiconductor wafer with an epitaxially deposited layer is more expensive and requires more complicated processing than does a standard wafer.
Consequently, the need exists for a cost-effective technique to maintain the noise performance of a semiconductor integrated circuit while reducing the number of power and ground bonding pads on the integrated circuit to thereby reduce the die size to provide cost savings. Reducing the number of bonding pads results in a reduced number of power and ground pins for the package, which provides an additional number of I/O pins for additional I/O signals or which provides an reduction in the silicon area used by an integrated circuit. It would be advantageous if improved performance was obtained while still using wirebonding techniques and without having to resort to more expensive packaging techniques such as flip chips, multilayer tape-automated-bonding, etc.